Appendix B
TMC2209 register cheat sheet
about 2 minutes
| Address | Name | R/W | Purpose |
|---|---|---|---|
| 0x00 | GCONF | RW | i_scale_analog b0, en_spreadcycle b2, shaft b3, index_step b6, mstep_reg_select b7 |
| 0x01 | GSTAT | R+clear | reset / drv_err / uv_cp flags |
| 0x02 | IFCNT | R | Increments on each successful write; use to verify the UART |
| 0x03 | SLAVECONF | W | Reply delay |
| 0x06 | IOIN | R | Live state of the input pins; also chip version |
| 0x10 | IHOLD_IRUN | W | IHOLD b0–4, IRUN b8–12, IHOLDDELAY b16–19 |
| 0x11 | TPOWERDOWN | W | Delay before dropping to hold current |
| 0x12 | TSTEP | R | Measured time between steps (larger = slower) |
| 0x13 | TPWMTHRS | W | StealthChop → SpreadCycle crossover velocity |
| 0x14 | TCOOLTHRS | W | Lower velocity limit for StallGuard and CoolStep |
| 0x22 | VACTUAL | W | Internal step generator — spin the motor without STEP pulses |
| 0x40 | SGTHRS | W | StallGuard threshold; stall when SG_RESULT ≤ 2 × SGTHRS |
| 0x41 | SG_RESULT | R | Load measurement, 0–510; high = light load |
| 0x42 | COOLCONF | W | CoolStep SEMIN, SEMAX, SEDN, SEUP |
| 0x6A | MSCNT | R | Microstep counter position |
| 0x6C | CHOPCONF | RW | TOFF b0–3, vsense b17, MRES b24–27, intpol b28 |
| 0x6F | DRV_STATUS | R | SG_RESULT b0–9, CS_ACTUAL b16–20, ot b25, otpw b26, stealth b30, stst b31, plus short and open-load flags |
| 0x70 | PWMCONF | RW | StealthChop configuration |
| 0x71 | PWM_SCALE | R | Current StealthChop scaling — useful diagnostic |
MRES encoding (note it counts down): 0 = 1/256, 1 = 1/128, 2 = 1/64, 3 = 1/32, 4 = 1/16, 5 = 1/8, 6 = 1/4, 7 = 1/2, 8 = full step.
Standalone MS1/MS2 microstep table: (MS2, MS1) = (0,0) → 1/8, (0,1) → 1/2, (1,0) → 1/4, (1,1) → 1/16.
UART addressing: MS1 is address bit 0, MS2 is address bit 1. Four drivers maximum per UART line.
Datagram formats: write = 0x05, addr, reg|0x80, data[4], CRC (8 bytes). Read request = 0x05, addr, reg, CRC (4 bytes). Read reply = 0x05, 0xFF, reg, data[4], CRC (8 bytes). CRC-8, polynomial 0x07, LSB-first.